1. Field of the Invention
The present invention relates generally to a stabilized direct sensing memory architecture, and more particularly pertains to a stabilized direct sense memory amplifier which comprises a common source NFET amplifier with an adjustable current source load provided by a PFET. The PFET current source is automatically adjusted to place the NFET amplifier in an operating range to provide maximum amplification of a small signal superimposed on a bitline precharge voltage. A mimic bias generator circuit provides this operating point adjustment, and realizes a direct, single-ended sensing operation using a small number of transistors.
The present invention also has general applicability to sense data firm a transmission line or from any type of memory cell and in general to any application where a small analog signal level needs to be converted to a full digital signal, such as in optical interface transmission systems.
2. Discussion of the Prior Art
Direct sensing schemes have advantages of density, stability against read disturbs from heavy datalines, elimination of capacitive line-to-line coupling and associated data pattern sensitivities, and other noise advantages. Direct sensing schemes rely on switching a static latch, or an inverter, or a simple FET device, in response to a transition between a xe2x80x981xe2x80x99 bitline voltage and a xe2x80x980xe2x80x99 bitline voltage. In a typical prior art inverter having a power supply voltage of 1.2 volts, the inverter will switch from a logical high to a logical low level with a change of about 200 mv to its gate voltage. Variations in the manufacturing processes can cause different cases ranging from nominal to extreme imbalances between an NFET beta and a PFET beta. The change in gate voltage (200 mv) needed to switch between an output high and low is somewhat independent of process and temperature variations, but the absolute DC voltage switch point can move several hundred millivolts over different process and temperature ranges. Switching an inverter with a range of switch points with a small bitline signal would require tight manufacturing tolerances and may have a limited process window.
Another limitation of the prior art is its voltage sensitivity as the power supply is lowered. As the power supply is lowered, the ability of the output inverter to output a correct logical xe2x80x981xe2x80x99 level degrades, with the OUT signal slowing down and eventually failing as Vdd is reduced from 1.2V to 0.9V, with typical bitline voltage levels of about 50 mV around a precharge voltage level. This sensitivity limits the operating voltage of a direct sensing scheme and results in reduced product quality level, reliability and operating ranges.
Temperature has a more severe effect on the ability of an inverter to sense a small input signal. If the bitline voltage is lowered from 1.2 volts to 1.1 volts to simulate a worst case xe2x80x981xe2x80x99 level, at low temperatures the difference between a xe2x80x981xe2x80x99 and xe2x80x980xe2x80x99 inverter input level is greatly reduced. This causes the output node to falsely output high levels for xe2x80x980xe2x80x99 data input at low temperatures. This is caused by drifting of the NFET""s Vt and beta relative to that of the PFET""s, and results in limited operating and temperature ranges.
Accordingly, it is a object of the present invention to provide a stabilized direct sensing memory architecture which provides Process, Voltage and Temperature (PVT) compensation to a direct sensing circuit to increase manufacturing yield, and to extend the operating voltage and temperature ranges thereof independently of manufacturing tolerances.